TSMC Finflex combines different transistor densities in the same circuit

When circuit makers such as TSMC, Samsung, and Intel develop a new manufacturing node, it is often done in conjunction with a series of different cell libraries specifically adapted for different applications. It could be, for example, a density library, focusing on both high transistor density and the highest possible power efficiency, but compromising the clock frequencies achieved. At the other end is the performance library, which compromises on density and power efficiency to instead achieve the highest possible performance over high clock frequencies.

During its science conference, TSMC is now revealing its concept finflex. Finflex was developed to allow the company’s customers to integrate different cell libraries when designing their circuits. The practical application could be, for example, hybrid designers, where high-performance processor cores that achieve high clock frequencies can use the performance library, while energy-saving cores can alternatively use the density library to get higher transistor density and better power efficiency. . All this can be done in a monolithic circle without the need to divide the design into segments.

Finflex is offered with TSMC’s N3 and N3E process and is offered as the 3-2 Fine, 2-2 Fine, and 2-1 Fine cell libraries. Among these, 3-2 Fin is the high-performance variant, which in its design provides the N3E with 33 percent higher performance and 12 percent lower power consumption compared to the current N5 node. In the second part of the spectrum, we find 2-1 fins, which give an 11 percent less performance boost than the N5, but still reduce power by up to 30 percent with significant improvements in transistor density.

The manufacturing process for TSMC N3 will be introduced during the second half of the year and the refined node N3E will follow in 2023. The company plans to scale down to 2nm at the end of 2024 with the N2 manufacturing process.