AMD will hold a trial court for the Radeon RX7000 “RDNA3” on November 3

Earlier in the fall, AMD introduced a new generation of processors in the Ryzen 7000 series, which introduced the Zen 4 architecture and took the step to 5nm. It’s long been known that news will be expected on the graphics card side as well, as Scott Herkelmann, AMD’s head of graphics, revealed the November 3 unveiling date.

Today, AMD announced the Together We Advance Games, a live event to reveal the next generation of AMD Radeon™ graphics. AMD executives will provide details of the new high-performance, energy-efficient AMD RDNA™ 3 architecture that will deliver new levels of performance, efficiency and functionality for gamers and content creators.

Unsurprisingly, it was confirmed in one press releasewhich reveals a live broadcast Stream Under the name “Together we develop our games”. An interesting detail here is the name that reminds us so much of the unveiling of the Ryzen 7000 – “Together we advance PCs”. In order for it to be a live event before an ordinary court, an extraordinary technical briefing was given, which might also be the case here.

AMD has kept its RDNA 3 cards close to its box and has only officially revealed an occasional detail. First of all, it will be a new architecture whose changes are expected to be larger than the changes from the first generation RDNA in the Radeon RX 5000 series to the next Radeon RX 6000 with RDNA 2. This also includes manufacturing at 5 nm – but only partially.

The new architecture is surrounded by chip-Design, which would be a more complex model on the part of the processor, based on the information available. What is certain is that the graphics circuit itself, which includes all the computation units, is manufactured using TSMC’s 5nm technology. Surrounding this belief are no less than six smaller circuits manufactured at 6nm, each with a 16MB cache and a 64-bit memory bus – totaling 96MB and 384-bit respectively for the Pioneer.

A total of seven individual circuits are then expected to be placed on a large substrate, and in practice a large piece of silicon is fabricated at 65 nm. It is a more elegant solution on the processor side that offers lower power consumption when sending data between circuits and provides lower latency, with the downside that it is more expensive. However, they are necessary because graphics computations are significantly more sensitive to latency on the processor side, with AMD masking latency with large L3 caches.

The event takes place on November 3 at 21:00 Swedish time and can be followed on the AMD official YouTube channel.